LS2085ARDB_2016_1216_1115
=========================
* MINOR_VER = 22 ("V1.22")

* ERRATA
  E29   - NOR/I2C resets are released after LS2085; should be
          before it.
  


LS2085ARDB_2016_1028_1604
=========================
* MINOR_VER = 21 ("V1.21")

* ENHANCEMENTS
  E26   - Implement 'cfg_rsp_dis' (IFC_ALE config pin).
  E25   - Support Rev F boards with QSPI mode.
  E27   - Support Rev F with additional PCB_REV[2] bit.
  E28   - Add new 'cfg_qspi_en' config pin.


LS2085ARDB_2016_0419_1513
=========================
* MINOR_VER = 20 ("V1.20")

* Internal restructuring allows clock to change earlier and also does not reset
  the clock chip unless SYSCLK is actually changed.  This allows a very rapid
  startup time.

* All internal timers redesigned to be more space-efficient, required to fit
  above logic in as the device is %96 full.

* Support for RST_MODE.  SW_SPARE2 serves as "SW_RST_MODE" and the switch is
  used to preset RST_CTL[RST_MD].  Details:

    +-------------+-------------------------------------------------------+
    |  SW_SPARE2  |   RST_MODE                                            |
    +-------------+-------------------------------------------------------+
    |       0     |   RESET_REQ_B ignored (default on V1.19 and earlier)  |
    +-------------+-------------------------------------------------------+
    |       1     |   RESET_REQ_B triggers reset                          |
    +-------------+-------------------------------------------------------+

  NOTE: Current u-boot images all write RST_CTL[RST_MD]=11 which enables resets.


* Support for over-temp through the W83793.  The over-temp fault is masked by
  default (write 0 to the MSB of ALARM to enable).



LS2085ARDB_2015_1223_1410
=========================
* MINOR_VER = 19 ("V1.19")

* Supports 133 MHz SYSCLK speeds.

* VPP is enabled before GVDD/VTT (per DDR4 specifications).

* QSPI is supported on the IFC bus, or through the FPGA for various
  SPI/QSPI evaluation tests.  This requires wiring (Q)SPI parts to the
  board, see various rework instructions for details.  To support this,
  SW_SPARE[3:4] are now defined as follows: 
    +-----------------+-------------------------+----------------------------------
    |  SW_SPARE[3:4]  |   QSPI_MODE             |
    +-----------------+-------------------------+----------------------------------
    |       00        |   Off (standard mode)   | Backward compatible mode.
    +-----------------+-------------------------+----------------------------------
    |       01        |   QSPI mode             | QSPI attached to IFC bus.
    |                 |                         | NOR is disabled.
    |                 |                         | NAND is on IFC_CS0 always.
    |                 |                         | CPLD registers are on IFC_CS2.
    +-----------------+-------------------------+----------------------------------
    |       10        |   SPI mode              | SPI attached to CPLD 3V pins.
    |                 |                         | CPLD translates 1.8V IFC to 3V SPI.
    |                 |                         | NOR is disabled.
    |                 |                         | CPLD registers are on IFC_CS2.
    +-----------------+-------------------------+----------------------------------
    |       11        |   reserved              | n/a
    +-----------------+-------------------------+----------------------------------
  

NOTE: The SI5341 requires additional PLL lock time while changing
      from 100 MHz, system startup is ~2 seconds slower now.


LS2085ARDB_2015_0519_1355
=========================
* MINOR_VER = 18
* For Rev D or later (PCB_REV[1:0] = 10 or 11), TESTSEL_B
  has changed. Now a switch is used to select the value, which
  is driven onto TESTSEL_B.
  The switch used has not changed: SW8#5 (Rev C or later).
* DUTCFG2[0] (TESTSEL) is now supported.


LS2085ARDB_2015_0414_1139
=========================
* MINOR_VER = 17
* For Rev D or later (PCB_REV[1:0] = 10 or 11), the 0.85V
  power supply was replaced and the "power good" signal is now
  active high.  PCB_REV is used to selectively invert the PG signal.



LS2085ARDB_2015_0213_1354
=========================
* MINOR_VER = 16
* Using RST[RST] or RCFG[GO] from CCS might trigger a "HRESET detected.."
  error, because reset started while CCS is polling SAP.  A 25ms delay
  was added before reset starts.
* RST_FORCE1[SLOTS] was not working (RST_FORCE2[SLOT1:SLOT2] does).
* RST_FORCE1[HRST] and RST_FORCE1[TRST] were not working; added.
* RST_FORCE1[PORST] was documented, however it was not intended to
  be supported.  Will be removed from spec, and bit 0 has no effect.


LS2085ARDB_2015_0211_0846
=========================
* MINOR_VER = 15
* BRDCFG2 was changed to correctly report 100 or 100SSCG for the
  SerDes2 clock speeds.
* NAND R/W data needs to be on AD[7:0] for the non-interposer case.
* RB_B assignment was incorrect; since IFC_CS_B[1] is not used, all
  devices use IFC_RB_B[0].  IFC_RB_B[1] is now unused.  Note that
  this can be changed using the IFC RB assignment register, but it
  is not the default.
* PCB_REV was internally expanded to 3 bits in case of extra board
  revisions.



LS2085ARDB_2015_0207_1558
=========================
* MINOR_VER = 14
* Correct register write issue when using LS2085A (interposer not
  affected).


LS2085ARDB_2015_0204_1157
=========================
* MINOR_VER = 13
* LS2085A does not output IFC_CLK, so no logic may use it.  Converted
  address sample into a latch.  Latches are OK on front-facing signals
  like IFC_AD.


LS2085ARDB_2015_0129_1018
=========================
* MINOR_VER = 12
* Fixes as issue where fast writes to RST[RST] or RCFG[GO] registers
  would not be seen.


LS2085ARDB_2015_0128_1051
=========================
* MINOR_VER = 11
* RST[RST] added for better uboot compatibility.


LS2085ARDB_2015_0120_1540
=========================
* MINOR_VER = 10
* RCFG.GO working.
* Fixed polarity of RSTSTAT.
* BRDCFG2 (SerDes speed) corrected to indicate 156.25 MHz fixed.
* BRDCFG5 defaults to 0x0A since SPI boot is the only valid boot
  preset.


LS2085ARDB_2015_0116_1302
=========================
* MINOR_VER = 9
* BRDCFG5 is preset based on SPI vs. SDHC selection of cfg_rcw_src.
* Direct control of Si5341 FINC/FDEC is possible through CLK_D1 bits.
* SW_SYSCLK sets nominal SYSCLK frequency.  Uboot is fixed SYSCLK=100
  currently so this can't be used.
* LBMAP corrected for NAND.
* CMSA/CMSD support for virtual switches added (except for those not
  connected).  Note the weird switch numbering on the RDB requires
  arbitrary renumbering:
        VSW1  = SW1
        VSW2  = SW10
        VSW3  = SW3
        VSW4  = SW4
        VSW5  = SW9
        VSW6  = SW6
        VSW7  = SW7
* Added BRDCFG1 as an alias of CLK_SPD1 to aid uboot compatibility.
* Changed clock tree internally.  Minor timing changes which should
  be invisible but reduces device to 82% full.

KNOWN ISSUES:
* RCFG.GO is not working.



LS2085ARDB_2015_0109_1338
=========================
* MINOR_VER = 8
* SD mux was moved to bits [7:6] to match documentation.
* RST_CTL changed to mask RESET_REQ_B by default.  Uboot needs to
  change this to use the conventional software reset first.
* Moved NAND to CS2 to match QDS software arch.
* Power-off IDLE mode changed to state = 0x01 so that AC on can be
  detected. 
* Thermal monitoring enabled for non-interposers.


LS2085ARDB_2015_0107_1613
=========================
* MINOR_VER = 7.
* QTAG (unused) is now a minor revision marker.  Requires manual control so
  not guaranteed to be unique.  
* RST_STAT added for debug.
* Changed Bank 2/3 default IO voltage to see if it helps (doesn't).
* Reversed VBANK bit-order to make switches easier to set.
* Added delay to POR sequence.



LS2085ARDB_2014_1219_1517
=========================
* MINOR_VER = 6.
* Corrects address multiplexing for NOR.


LS2085ARDB_2014_1219_1330
=========================
* MINOR_VER = 5.
* Passes simple R/W tests of BCSR space.
* OVDD (1.8V) is not monitored.



* Switch Usage
  SW_SPARE6 is now SW_TBSCAN_EN.  Set to 1(down).
  SW_SPARE5 is now SW_BYPASS.  Set to 1(DN) to disable thermal checks. 



Recommended Switch Settings
===========================
Requires RCW programmed to NOR.

(0=up 1=down)
SW7  = 11100110
SW6  = 01000111
SW9  = 00000000
SW3  = 10000001
SW10 = 00010111
SW1  = 11111111
SW4  = 11110010

Untested
========
* NAND
* Reconfiguration
